About

Hello! I’m Minbok Wi.

I am a Staff Engineer in the AP Architecture Group (MX Division) at Samsung Electronics. As a performance architect, I model and develop the subsystems of mobile Application Processors (SoCs): driving architecture definition, analyzing workload performance to remove system-level bottlenecks, and maximizing power efficiency for next-generation mobile platforms.

I received my Ph.D. from Seoul National University, where I was advised by Prof. Jung Ho Ahn. During my doctoral studies, I spent time as a Visiting Scholar at UT Austin, collaborating with Prof. Mattan Erez. My doctoral research centered on the security, reliability, and characterization of DRAM-based memory systems.

Research

My work spans computer architecture, memory architecture & systems, and hardware security & reliability.

• Computer architecture: architectural modeling and performance optimization of processor and system-on-chip subsystems across CPU, interconnect, and memory; system-level bottleneck analysis and power-efficiency trade-offs. In my current role at Samsung, this focuses on mobile Application Processors (SoCs).
• Memory architecture & systems: DRAM microarchitecture, address mapping, and timing behavior; memory-subsystem performance; emerging memory interfaces such as CXL.
• Hardware security & reliability: RowHammer and DRAM disturbance attacks and their mitigations; DRAM reverse-engineering through direct command issuing; reliable and secure memory design (on-die ECC, CXL memory).

Full publication record on Google Scholar.

Publications

[ISCA26] Jumin Kim*, Seungmin Baek*, Hwayong Nam, Minbok Wi, Nam Sung Kim, Jung Ho Ahn, “PVAC: A RowHammer Mitigation Architecture Exploiting Per-victim-row Counting,” ISCA, 2026 (*co-first author)

[Access26] Minbok Wi*, Wanju Doh*, Seungmin Baek, Seonyong Park, Mattan Erez, Jung Ho Ahn, “Sudoku: Refining DRAM Address Mapping through Advanced Timing and Configuration Analysis,” IEEE Access, 2026 (*co-first author)

[ASPLOS26] Minbok Wi, Yoonyul Yoo, Yoojin Kim, Jaeho Shin, Jumin Kim, Yesin Ryu, Saeid Gorgin, Jung Ho Ahn, Jungrae Kim, “RowArmor: Efficient and Comprehensive Protection Against DRAM Disturbance Attacks,” ASPLOS, 2026 [Best Paper Honorable Mention]

[HPCA26] Chihun Song, Austin Antony Cruz, Michael Jaemin Kim, Minbok Wi, Gaohan Ye, Kyungsan Kim, Sangyeol Lee, Jung Ho Ahn, and Nam Sung Kim, “ReScue: Reliable and Secure CXL Memory,” HPCA, 2026

[CAL25] Jumin Kim, Seungmin Baek, Minbok Wi, Hwayong Nam, Michael Jaemin Kim, Sukhan Lee, Kyomin Sohn, and Jung Ho Ahn, “Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads,” IEEE Computer Architecture Letters (Volume: 24, Issue: 2, July-Dec. 2025): 217-220 [Best of CAL]

[DRAMSec25] Minbok Wi, Seungmin Baek, Seonyong Park, Mattan Erez, and Jung Ho Ahn, “Sudoku: Decomposing DRAM Address Mapping into Component Functions,” DRAMSec, 2025

[ASPLOS25] Seungmin Baek, Minbok Wi, Seonyong Park, Hwayong Nam, Michael Jaemin Kim, Nam Sung Kim, Jung Ho Ahn, “Marionette: A RowHammer Attack via Row Coupling,” ASPLOS, 2025

[ISCA24] Hwayong Nam, Seungmin Baek, Minbok Wi, Michael Jaemin Kim, Jaehyun Park, Chihun Song, Nam Sung Kim, Jung Ho Ahn, “DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands,” ISCA, 2024

[ASPLOS24] Chihun Song, Michael Jaemin Kim, Tianchen Wang, Houxiang Ji, Jinghan Huang, Ipoom Jeong, Jaehyun Park, Hwayong Nam, Minbok Wi, Jung Ho Ahn, Nam Sung Kim, “TAROT: A CXL SmartNIC-Based Defense Against Multi-bit Errors by Row-Hammer Attacks,” ASPLOS, 2024

[CAL23] Hwayong Nam, Seungmin Baek, Minbok Wi, Michael Jaemin Kim, Jaehyun Park, Chihun Song, Nam Sung Kim, Jung Ho Ahn, “X-ray: Discovering DRAM Internal Structure and Error Characteristics by Issuing Memory Commands,” IEEE Computer Architecture Letters (Volume: 22, Issue: 2, July-Dec. 2023): 89-92

[MICRO23] Michael Jaemin Kim, Minbok Wi, Jaehyun Park, Seoyoung Ko, Jaewan Choi, Hwayong Nam, Nam Sung Kim, Jung Ho Ahn, Eojin Lee, “How to Kill the Second Bird with One ECC: The Pursuit of Row Hammer Resilient DRAM,” MICRO, 2023

[HPCA23] Minbok Wi*, Jaehyun Park*, Seoyoung Ko, Michael Jaemin Kim, Nam Sung Kim, Eojin Lee, Jung Ho Ahn, “SHADOW: Preventing Row Hammer in DRAM using Intra-Subarray Row-Shuffling,” HPCA, 2023 (*equally contributed)

[TC20] Byeongho Kim, Jongwook Chung, Eojin Lee, Wonkyung Jung, Sunjung Lee, Jaewan Choi, Jaehyun Park, Minbok Wi, Sukhan Lee, Jung Ho Ahn, “MViD: Sparse Matrix-Vector Multiplication in Mobile DRAM for Accelerating Recurrent Neural Networks,” IEEE Transactions on Computers (Volume: 69, Issue: 7, 01 July 2020): 955-967